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It is anticipated that the mass production of 2nm process technology is about a year away. At present, for TSMC, Samsung, and Intel, these three major players have all entered the trial production preparation phase, and a new round of competition for the advanced process market is imminent.

After years of technological accumulation, development, and catching up, the gap between Samsung, Intel, and TSMC in terms of process maturity and yield is becoming smaller and smaller. In the 2nm era, TSMC is expected to still occupy an advantageous position, but compared with the 5nm and 3nm periods, the market competition is likely to be much more intense.

01

The 2nm Technology Roadmap of the Three Major Players

In the development of 2nm process technology, TSMC, Samsung, and Intel have both similarities and differences. Overall, TSMC is relatively stable, Intel is relatively aggressive, and Samsung is in a middle position.

Let's first look at TSMC.

The wafer foundry leader's 2nm process will include three versions: N2, N2P, and N2X. It is expected to start mass-producing the first generation of GAAFET N2 node chips in the second half of 2025, and the next version of 2nm, N2P, will be mass-produced at the end of 2026. Unlike Intel, TSMC's two versions of 2nm processes do not use backside power supply technology. However, the entire N2 series will add TSMC's new NanoFlex feature, which allows chip designers to match cells from different libraries (high-performance, low-power, different areas) in the same module to improve performance or reduce power consumption.

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To control costs, TSMC will use the GAAFET transistor architecture, instead of the rumored complementary field-effect transistor (CFET).TSMC's 3nm process already supports a feature called FinFlex, which also allows designers to use cells from different libraries. However, N2 relies on GAAFET nanosheet transistors, enabling NanoFlex to provide some additional control capabilities that can optimize the channel width for performance and power.

Compared to N3E, TSMC expects N2 to improve performance by 10% to 15% at the same power, or reduce power consumption by 25% to 30% at the same frequency and complexity.

After N2, there will be the performance-enhanced N2P, followed by the voltage-enhanced N2X in 2026. Although TSMC had previously stated that N2P would add a backside power delivery network (BSPDN) in 2026, it seems that this is not the case. N2P will use conventional power supply circuits for reasons that are not yet clear.

N2 is still expected to adopt innovations related to power, namely the Super High-Performance Metal-Insulator-Metal (SHPMIM) capacitor, which can improve power supply stability. The capacitance density of the SHPMIM capacitor is more than twice that of TSMC's existing Super High-Density Metal-Insulator-Metal (SHDMIM) capacitors.

Now, let's look at Samsung.

Samsung will also start mass-producing 2nm (SF2) process chips in 2025, followed by the adoption of backside power delivery technology in 2026. Compared to the 3nm process (SF3), Samsung's 2nm process offers a 12% performance improvement, a 25% power efficiency improvement, and a 5% area reduction.

Relative to TSMC, Samsung has not disclosed many details about its 2nm process technology, and it is unclear whether there will be any major breakthroughs when mass production begins.

Finally, let's look at Intel.

In early 2024, when announcing its "five nodes in four years" plan (called "5N4Y"), Intel introduced its 20A (2nm-class) process technology, which is scheduled to enter production in early 2025.It is reported that Intel's 20A has introduced RibbonFET GAA transistors and PowerVia backside power delivery technology, while the subsequent upgrade version 18A will further improve these two technologies. The company is an active advocate of backside power delivery technology and is continuously improving it, so it is expected that Intel will also have a lot of innovation in the field of 2nm process technology.

Intel will use backside power delivery technology two years earlier than TSMC, and in terms of using GAA transistor architecture, it is also a year and a half earlier than TSMC. However, whether these new technologies can be transformed into tangible mass production advantages depends on whether Intel can optimize PPA (performance, power consumption, area) in place.

02

Digital Games

In March 2024, Samsung Electronics notified customers and partners, announcing that the new second-generation 3nm process will be renamed to 2nm. Samsung said that the process will be mass-produced by the end of this year.

An IC design industry insider said: "We received a notice from Samsung Electronics that they are renaming the second-generation 3nm process to 2nm. The second-generation 3nm process contract we signed with Samsung Electronics foundry last year will also be renamed to 2nm, so we need to rewrite the contract in the near future."

Some insiders said that Samsung's second-generation 3nm process reduced the size of transistors, largely to meet marketing needs.

TSMC revealed at the IEEE International Electron Devices Meeting (IEDM) that it will launch a 1.4nm process after 2nm, and continue to officially name the 2nm as A20, the 1.4nm is named A14, and is expected to be mass-produced between 2027 and 2028.

Samsung is closely following TSMC and announced plans to mass-produce a 1.4nm process in 2027.

Intel's naming of the process has changed from the "stubbornness" of many years ago, no longer sticking to the absolute standards of Moore's Law, but considering more commercial expansion needs, making the process node sound closer to the market and customer habits. Therefore, the company's CEO, Gelsinger, reiterated at the Intel Innovation Day in Taipei that Intel 7 has entered the mass production stage, Intel 4 is now ready for mass production, and Intel 3 will be launched as scheduled by the end of this year. He demonstrated the wafers produced by Intel 20A on the spot, which are expected to be used for the Arrow Lake processor to be launched in 2025, and Intel 18A is also expected to enter the mass production stage in the second half of 2025.Currently, for advanced process technologies of 5nm and below, there is an increasing number of "digital games," which are also a product of competitive pressure. Due to TSMC's advanced processes being deeply rooted in the industry, in order to enhance competitiveness and gain more market share, it is necessary to adapt to market demands and customer habits, which will help expand market space.

03

Challenges of 2nm process mass production

The year 2025 is the first year of mass production of the 2nm process, and the real competition is likely to emerge in 2026. For TSMC, Samsung, Intel, and Japan's Rapidus, they still need to solve their respective problems to carry out mass production work.

TSMC's high cost

Analysts at International Business Strategies (IBS) believe that compared to 3nm processors, the cost of 2nm chips will increase by about 50%.

IBS estimates that the cost of a 2nm production line with a capacity of about 50,000 wafers per month (WSPM) is about 28 billion US dollars, while the cost of a 3nm production line with similar capacity is about 20 billion US dollars. A large part of the increased cost comes from the increase in the number of EUV lithography equipment, which will greatly increase the production cost per wafer and per chip. Only a few manufacturers such as Apple, AMD, NVIDIA, and Qualcomm can accept such high-cost chips.

IBS estimates that in 2025-2026, using TSMC's N2 process to process a single 12-inch wafer will cost Apple about 30,000 US dollars, while the wafer cost based on the N3 process is about 20,000 US dollars.

With the increasing demand for AI processors, NVIDIA's share of TSMC's revenue will increase in 2024. The company has already booked TSMC's wafer foundry and CoWoS packaging capacity to ensure a stable supply of high-quality processors for AI. This year, AMD's share of TSMC's total revenue is expected to exceed 10%.

It is precisely because of large customers such as Apple, NVIDIA, and AMD placing orders that TSMC will invest in the most advanced processes on a large scale. Otherwise, it is difficult to sustain the production line of such a money-burning process like 2nm. However, given the current situation, TSMC's forecast for the 2024 full-year wafer foundry market is relatively conservative, believing that the previous estimate was too optimistic. The previous estimate was that the industry would grow by about 20% per year, but now it seems that the growth rate may only be about 10%. Under these circumstances, even with large customer orders, it is necessary to control costs and capital expenditure.Currently, TSMC is exerting comprehensive cost control, including expenditure on EUV equipment and energy conservation. Although other manufacturers will also face cost issues in the 2nm process, Samsung and Intel seem less sensitive to cost in order to catch up with TSMC. In addition, TSMC's plan to build at least two advanced process wafer fabs in the United States has brought it a lot of additional cost pressure. Therefore, TSMC's 2nm process production line must be meticulously planned.

Samsung's Yield Issues

For wafer foundries, yield is very important as it directly affects production costs and customer recognition.

Since entering the 5nm process era, yield has been the biggest problem faced by Samsung's wafer foundry business, especially at the 3nm process node, where Samsung took the lead in introducing a brand new GAA (Gate-All-Around) transistor architecture, which is quite different from the previously used FinFET transistors, further amplifying the yield issue.

According to Notebookcheck, Samsung's 3nm process yield is hovering around 50%, with some issues still to be resolved. Samsung stated in 2023 that the yield of its 3nm process had reached over 60% after mass production, but now it seems to have been overly optimistic at that time.

In February of this year, according to South Korean media reports, Samsung's new 3nm process has significant issues, with all trial production chips having defects and a yield of 0%. The report pointed out that the Exynos 2500 chip using the 3nm process failed the quality test due to defects, resulting in the inability to mass-produce the subsequent Galaxy Watch 7 chipset. The report stated that due to the failure of the Exynos 2500 chip trial production, Samsung postponed mass production, and it is currently unclear whether the yield issue can be resolved in time.

In order to catch up with TSMC, Samsung's 3nm process technology has adopted a more aggressive strategy, mainly reflected in the GAA transistor architecture, while TSMC's 3nm still uses FinFET. It will only switch to GAA transistors at 2nm, and the result of being aggressive is to pay some price in yield.

If the yield issue of 3nm cannot be resolved, the same problem may occur at 2nm.

Intel's Customers

For a new entrant in the wafer foundry industry, the biggest problem Intel faces is, of course, customer recognition, especially for advanced process technologies like 2nm. For manufacturers with little mass production experience and shipment volume in the wafer foundry market below 10nm, how to seize customers, especially those with large shipment requirements (2nm costs are very high, and if the shipment volume is small, it is not possible to make a profit), in competition with TSMC and Samsung, is a big challenge.Challenges for Rapidus

The 2nm process technology of Japan's Rapidus semiconductor foundry originates from IBM. Rapidus has dispatched engineers to IBM's Albany Nanotech Center in New York for research and development, and is collaborating with partners other than IBM to develop the 2nm process, with the goal of mass production in the late 2020s.

Similar to Intel, Rapidus is a new entrant in the semiconductor foundry industry, and the development of large-scale production processes starts from scratch, with customer recognition being a major challenge.

Assuming that companies such as Toyota Motor, Denso, NTT, and IBM, which have invested in Rapidus, will entrust Rapidus with the production of advanced process chips they need, but how many 2nm process chips will these manufacturers demand? Customers who outsource advanced process chips to foundries like TSMC and Samsung, such as Apple, Qualcomm, AMD, Nvidia, and MediaTek, are the major shippers. Whether they can choose Rapidus depends on whether these major customers can fully understand and recognize Rapidus's process level and the added value it creates. If they cannot, it will be difficult for them to transfer orders from TSMC and Samsung.

Moreover, merely learning IBM's 2nm process in Albany does not mean it can be directly applied to the mass production of Rapidus's foundry, as many engineering issues need to be resolved, and this is not something that can be achieved overnight.

Another issue is how many EUV equipment Rapidus can obtain, which is crucial for the mass production of 2nm process chips. ASML's shipments of EUV lithography equipment in 2022 were about 55 units, and the production capacity in 2023 increased to more than 60 units, with the potential to reach around 90 units by 2025. However, as the feature size of the process technology becomes smaller and smaller, the number of EUV lithography layers will continue to increase, and other foundries will continue to compete for EUV equipment. How much can Rapidus get?

Conclusion

According to South Korean media reports, TSMC President CC Wei did not attend the TSMC 2024 Technology Forum held in Taipei on the 23rd because he went to Europe for a secret visit to ASML's headquarters in the Netherlands and the German industrial laser company TRUMPF.

In order to sprint in advanced process semiconductor foundry, Intel has become the first buyer of ASML's latest High-NA EUV (high numerical aperture EUV lithography machine). TSMC's senior management originally stated that its 2nm and A16 process nodes do not need High-NA EUV because it is too expensive. However, according to BusinessKorea, TSMC President CC Wei's secret flight to the Netherlands this time is to discuss EUV equipment matters with ASML.Although the details of Wei Zhejia's visit to Europe were kept confidential, the new CEO of ASML, Christophe Fouquet, and the CEO of TRUMPF, Nicola Leibinger-Kammüller, both revealed the news of Wei Zhejia's visit on social media. Fouquet stated outright that ASML introduced to Wei Zhejia the company's latest technologies and products, including how the High-NA EUV equipment will realize the micro-fabrication process technology of future semiconductors.

This can reflect from one aspect that the competition for the new generation of lithography equipment among TSMC, Intel, and Samsung is heating up, and the race for advanced processes of 2nm and below has already begun.