tech

Samsung has neither secured large-volume orders from customers, nor has it escaped the dual blow from Intel and TSMC in the field of advanced manufacturing processes.

Semiconductor foundries began to compete in the 2nm process shortly after starting mass production for customers on the 3nm production line. In June 2022, Samsung took the lead in producing 3nm wafers using the gate-all-around (GAA) architecture, which is worth learning from.

Two years have passed, and Samsung's ambition to surpass TSMC with GAA has not been successful. Samsung has neither secured large-volume orders from customers, nor has it escaped the dual blow from Intel and TSMC in the field of advanced manufacturing processes.

Although there have been rumors for a long time that Samsung provides 3nm process services for AMD, AMD CEO Lisa Su emphasized at the 2024 Taipei International Computer Show that the company is still cooperating with TSMC. From the recent conversation between TSMC Co-Chief Operating Officer YJ Mii and AMD CTO Mark Papermaster, it is not difficult to see how difficult it is to snatch advanced process orders from competitors.

Advanced processes highlight that traditional scaling methods are no longer sufficient, and foundries can no longer achieve 2nm or even more advanced processes by working behind closed doors. Instead, as Papermaster said, TSMC's emphasis on Design-Technology Co-Optimization (DTCO) has played a more important role.

Advertisement

Papermaster said that since the 2010s, the traditional cooperation model between foundries and IC designers has become increasingly insufficient. He emphasized that TSMC's emphasis on DTCO can help customers make full use of their wafers in various ways.

DTCO, as the name suggests, is the comprehensive optimization of design and process technology to improve performance, power efficiency, chip density, and cost. TSMC has previously stated that the process development team and the design development team must cooperate from the beginning to optimize the design technology synergy for the next generation of technology, exploring the possibilities of design innovation and process capabilities.DTCO helps identify overly extreme and worthless process routes, focusing on customer needs and reducing development pressure; on the other hand, DTCO can help customers find a balance between performance, power consumption, and wafer area, which is difficult to achieve solely by process miniaturization; in addition, DTCO helps to leverage the technical potential of a single node.

DTCO also comprehensively examines how wafer devices interact with each other and how to meet multiple requirements simultaneously, and urges foundries to find new methods for manufacturing wafer devices, to promote the transition from planar transistors to FinFET transistors as key components. These explorations and engineering experiences will affect the timing of the introduction of GAA transistors and CFET transistors.

In the communication, Yujie Mee also mentioned the difficulty of 2nm, and as the scale of advanced processes expands, the challenge of scaling down also increases, but he believes that there is still room for growth after 2nm, and the key to success lies in cooperation with customers.

The dialogue between Papermaster and Yujie Mee also emphasized the increasing importance of DTCO with the introduction of GAA.

The GAA transistor architecture can be transformed into higher performance, lower power consumption, and more optimized chip design. After Samsung took the lead in introducing GAA in the 3nm era, if it can find a long-term partner for bidirectional cooperation between design and process, it will undoubtedly take a leading step in obtaining better GAA transistor yield.

AMD switched from GlobalFoundries to TSMC in 2018 to manufacture its chips below 7nm. The AMD team has been working with TSMC on the Zen architecture process blueprint from an early stage. AMD recently released the Zen 5 CPU at Computex, but it has confirmed that it will adopt 4-nanometer and 3-nanometer technology no earlier than 2022, and its DTCO process with TSMC should happen earlier.

TSMC 2nm process

TSMC provided several important updates on its upcoming process technology at its 2024 North American Technology Symposium. Overall, TSMC's 2-nanometer plan remains basically unchanged: the company is expected to start mass production of chips on its first-generation GAAFET N2 node in the second half of 2025, and N2P will succeed N2 at the end of 2026, although without the previously announced back power supply function. At the same time, the entire N2 series will add TSMC's brand-new NanoFlex feature, which allows chip designers to mix and match cells from different libraries to optimize performance, power, and area (PPA).One of the significant announcements at this press conference was TSMC's NanoFlex technology, which will become part of the company's complete N2 series production nodes (2-nanometer, N2, N2P, N2X). NanoFlex will enable chip designers to mix and match cells from different libraries (high-performance, low-power, area-efficient) in the same design, allowing designers to fine-tune their chip designs to improve performance or reduce power consumption.

TSMC's current N3 manufacturing process already supports a similar feature called FinFlex, which also allows designers to use cells from different libraries. However, since N2 relies on all-around gate (GAAFET) nanosheet transistors, NanoFlex provides TSMC with some additional control: TSMC can optimize channel width to improve performance and power, then build short cells (to improve area and power efficiency) or tall cells (to improve performance by 15%).

Speaking of timing, TSMC's N2 will enter risk production in 2025 and enter high-volume manufacturing (HVM) in the second half of 2025, so it seems we will see N2 chips in retail devices in 2026.

Compared to N3E, TSMC expects N2 to improve performance by 10% to 15% at the same power, or reduce power consumption by 25% to 30% at the same frequency and complexity. As for chip density, the foundry is considering increasing the density by 15%, which is a good expansion compared to contemporary standards.

Following N2, the performance-enhanced N2P and voltage-enhanced N2X will emerge in 2026. Although TSMC had indicated that N2P would add a backside power delivery network (BSPDN) in 2026, it seems this is not the case, and N2P will use conventional power circuits. The reason is unclear, but it appears the company decided not to add the expensive feature to N2P and instead reserve it for the next-generation node, which will also be available to customers by the end of 2026.

N2 is still expected to achieve a significant innovation in power: ultra-high-performance metal-insulator-metal (SHPMIM) capacitors, which are added to improve power supply stability. The capacitance density of SHPMIM capacitors is more than double that of TSMC's existing ultra-high-density metal-insulator-metal (SHDMIM) capacitors. In addition, compared to the previous generation, the new SHPMIM capacitors have reduced sheet resistance (Rs, in ohms per square) and via resistance (Rc) by 50%.