Achieving Smaller, Faster Transistors at an Unprecedented Speed.
ASML announced at the imec ITF World 2024 conference that its first High-NA equipment has now set a new record for chip manufacturing density, surpassing the record set just two months prior. Former ASML President and Chief Technology Officer Martin van den Brink, who now serves in a consulting role for the company, has also proposed that the company could develop a Hyper-NA chip manufacturing equipment to further expand its High-NA product line and shared a roadmap. He outlined a plan to reduce the cost of EUV chip manufacturing by fundamentally doubling the speed of future ASML tools to 400-500 wafers per hour (wph), more than double the current peak of 200 wph. He also proposed a modular unified design for ASML's future EUV equipment.
Van der Brink stated that, with further adjustments, ASML has already imprinted integrated circuits with a resolution of 8nm using its high numerical aperture EUV equipment, breaking the company's record set in early April when the company announced that its High-NA equipment had imprinted 10nm resolution products in the joint laboratory with imec at ASML's headquarters in Veldhoven, the Netherlands.
ASML's standard Low-NA EUV equipment can imprint feature sizes of 13.5nm, while the new High-NA EXE:5200 EUV tool is designed to create smaller transistors by imprinting 8nm feature sizes.
Advertisement
"Today, we have made progress, and we are able to display record imaging as low as 8nm across the entire field, and there is still some degree of overlay," Van der Brink said, "By the way, this is not perfect data, but it shows progress."
This milestone represents the culmination of more than 10 years of R&D and investment of billions of euros, but there is still more work to be done to optimize the system and prepare it for mass production for major chip manufacturers. This work is already underway in the Netherlands, and Intel is the only chip manufacturer that has fully assembled a high numerical aperture system, following closely behind ASML and putting its own equipment into operation at its D1X wafer plant in Oregon, USA. Intel will first use its EXE:5200 High-NA equipment for R&D purposes, and then for the production of its 14A process node.
Van der Brink also proposed a new Hyper-NA EUV equipment, but no final decision has been made on this equipment yet - ASML seems to be gauging industry interest, and only time will tell if it can be realized.Today's standard EUV equipment uses light with a wavelength of 13.5nm and a numerical aperture (NA, a measure of the ability to collect and focus light) of 0.33. In contrast, the new high-NA equipment uses the same light wavelength but adopts a 0.55 NA to engrave smaller feature sizes. Van der Brink's proposed Hyper-NA system will once again use light of the same wavelength, but will expand the NA to 0.75 to print even smaller feature sizes. We are not sure about the suggested critical dimensions, but ASML's transistor roadmap shows that it is extending from a 16nm metal pitch to 10nm.
According to the roadmap, Hyper-NA may be feasible for single-exposure 2DFET transistors, but it is currently unclear whether High-NA with multi-patterning can also produce such fine pitches.
This machine will not appear until 2033. Today's high-NA equipment already costs about $400 million. Due to the need for larger, more advanced mirrors and improved illuminator systems, Hyper-NA products will be a more expensive option.
Like its predecessor, the goal of Hyper-NA is to print smaller feature sizes with a single exposure to avoid multi-patterning techniques (multiple exposures of the same area), which tend to increase the time and steps of the chip manufacturing process, as well as the probability of defects, all of which increase costs. Van Der Brink said that the continued development of photoresists and advanced masks will be key to improving feature resolution. Hyper-NA will also use an improved illumination system to achieve the best results. ASML did not elaborate, but it is logical that the improved illuminator will be paired with a higher power light source to help increase the dose, offset the higher mirror angles used for 0.75 NA, and improve throughput.
Van der Brink also proposed to increase the throughput of the company's future equipment from the current ~200 wph to 400-500 wph. This is another lever for ASML to control costs, in response to the trend of increasing prices per transistor for each new generation of chips.
To accelerate development and reduce costs, ASML has already used its existing Low-NA Twinscan NXE:3600 EUV equipment as a building block for its new High-NA products. ASML's Low-NA model adopts a modular design, allowing the company to use mature technologies and modules for its new tools, and the company only adds new modules when necessary.
However, there is still more room for optimization. Van der Brink believes that the company will redouble its efforts on the modular design concept in the next decade, creating new tools. The proposed long-term roadmap shows that Low-NA, High-NA, and Hyper-NA all have increasingly common modular platforms and shared components. This design is another lever for ASML to control costs.
The chip industry seems to have paved the way for future development, building gate-all-around (GAA) and complementary field-effect transistors (CFET) with low and high numerical aperture tools, but there is no real candidate to support the technology of future process nodes except for Hyper-NA. As always, cost will be a key factor, but ASML is obviously considering how to make the Hyper-NA pricing equation more attractive to its customers.
